1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device.
2. Description of Related Art
An EEPROM (also abbreviated as E.sup.2 PROM) is a semiconductor, nonvolatile, programmable read-only memory whose contents can be electrically erased and then selectively rewritten without having to remove it from its host circuit board. Because it is easily erased and programmed, the EEPROM can be more versatilely used in computers and various other intelligent electronic devices besides other types of ROMs. Conventional EEPORM devices are typically constructed based on a floating-gate structure. With EEPROM, the data erasure and reprogramming operation can be carried out in a bit-by-bit manner, typically at an access speed (access time) within the range of 150-200 ns (nanoseconds). Newer EEPROMs developed by the Intel Corporation of America, called flash EEPROMs, have an even higher access speed within the range of 70-80 ns.
A conventional flash EEPROM device is illustratively depicted in the following with reference to FIG. 1 FIGS. 1A-1C, and FIG. 2. FIG. 1 shows a schematic top view of the conventional flash EEPROM device and FIGS. 1A, 1B, and 1C are three different cross-sectional views of the flash EEPROM device of FIG. 1 respectively cutting through the lines I--I, II--II, and III--III.
Referring to FIG. 1 together with FIGS. 1A, 1B, and 1C, this conventional flash EEPROM device is constructed on a semiconductor substrate 100. In this flash EEPROM device, each memory cell is based on a MOS transistor element (called a floating-gate transistor) that is composed of a tunnel oxide layer 104, a floating gate 106, a dielectric layer 108, a control gate 110, a source region 112, and a drain region 114. The floating gate 106 is so named due to the fact that it is physically but not electrically isolated from all the other conductive elements in the flash EEPROM device. The floating gate 106 is located beneath the control gate 110 and isolated by the dielectric layer 108 from the control gate 110. The control gate 110 is electrically connected to one word line (not shown) of the flash EEPROM device.
The floating-gate transistor of each MOS memory cell of the flash EEPROM device can be operated in various ways. The following describes one of them. To write data into memory cell, the first step is to apply a drain voltage to the drain region 114 while applying a gate voltage, which is higher than the drain voltage, to the control gate 110. This action causes hot electrons to be emitted from the source region 112 and then pass through the channel to the drain region 114. Since these hot electrons are very high in energy, they can penetrate through the tunnel oxide layer 104 into the floating gate 106 to be trapped in the floating gate 106, thus causing an increase in the threshold voltage of the floating gate 106. This effectively sets the MOS memory cell to a state that represents the storage of a value of binary data into the MOS memory cell. On the other hand, when the data currently stored in the MOS memory cell needs to be erased, a reverse voltage is applied to the source region 112 to cause the electrons trapped in the floating gate 106 to be pulled out of the floating gate 106 through the tunnel oxide layer 104, thus causing the threshold voltage of the floating gate 106 to be lowered to the original level, effectively setting the MOS memory cell back to the original state.
To fabricate the foregoing flash EEPROM device, the first step is to perform a LOCOS (local oxidation of silicon) process on the substrate 100 so as to form a plurality of field oxide isolation layers 102 at selected locations to define the active regions where the MOS memory cells of the flash EEPROM device are to be formed. In subsequent steps, an oxide layer is formed and selectively removed to form the tunnel oxide layer 104; a first polysilicon layer is formed and selectively removed to form the floating gate 106; a dielectric layer is formed and selectively removed to form the dielectric layer 108; and a second polysilicon layer is formed and selectively removed to form the control gate 110. After this, with the polysilicon-based control gate 110 serving as a mask, an ion implantation process is performed on the wafer to dope an impurity element into the unmasked portions of the substrate 100, whereby the source region 112 and the drain region 114 are formed in the substrate 100. Subsequently, an insulating layer is formed and then etched back to form the sidewall spacers 116 on the sidewalls of the stacked structure of the tunnel oxide layer 104, the floating gate 106, the dielectric layer 108, and the control gate 110. After this, each field oxide isolation layer 102 between neighboring pair of source regions 112 is removed, leaving a void portion 150 in the wafer. Next, an ion-implantation process is performed to dope an impurity element through the void portion 150 into the exposed part of the substrate 100, whereby a self-aligned source region 118 is formed in the substrate 100. As shown in FIG. 1C, each self-aligned source region 118 is connected to each of the neighboring pair of the source regions 112.
The use of the LOCOS technique in the foregoing process, however, can cause a stress problem and a bird's beak problem. These two problems can cause the isolation structures to be less effective when the flash EEPROM device is further downsized for high-density integration, particularly at the submicron level of integration below 0.25 .mu.m (micrometers). One solution to these problems is to utilize the so-called shallow-trench isolation (STI) structure in lieu of the LOCOS structure.
However, the use of the STI technique in the process for fabricating the foregoing flash EEPROM device still has one drawback. This drawback will be depicted in the following with reference to FIG. 2, which is a schematic cross-sectional view of the flash EEPROM device of FIG. 1 cutting through the line III--III (the same view as FIG. 1C except when fabricated with the STI technique). As shown, if the STI technique is used to form the field oxide layers 102, it allows the ion-implantation process used to form the self-aligned source region (here designated by the reference numeral 118a for distinguishing purpose) to dope the impurity element only into the bottom part 160a of the void portion (here designated by the reference numeral 160) that is left behind by removing the field oxide isolation layers 102. Scarcely any of the impurity element is doped into the sidewalls 160b of the void portion 160. As a consequence, the resultant self-aligned source region 118a is not connected to the neighboring pair of the source regions 112. For this reason, the use of STI technique in the process for fabricating a flash EEPROM device is unfeasible.